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The present application relates generally to signal processing, and more specifically to improved systems and methods of performing sigma-delta modulation.
Sigma-delta modulators are known that may be employed in signal processors such as Digital-to-Analog Converters (DACs). For example, a conventional sigma-delta DAC typically comprises a digital sigma-delta modulator including a sigma-delta core circuit and a quantizer, and an internal DAC. In a normal mode of operation, the sigma-delta core circuit receives a digital input signal and provides its output to the quantizer, which in turn provides its output directly to the internal DAC and to the sigma-delta core via a feedback path. The sigma-delta modulator quantizes the digital input signal to a predetermined number of quantization levels. Specifically, the sigma-delta core circuit subtracts the output of the quantizer from the digital input signal, and outputs a representation of the sum of its previous input and its previous output. The quantizer then generates the appropriate quantization level based on the output provided to it by the sigma-delta core circuit. Finally, the internal DAC receives the quantization levels from the quantizer, and produces an analog output signal therefrom corresponding to the digital input signal.
The conventional sigma-delta DAC may be configured as a single-bit sigma-delta DAC or a multi-bit sigma-delta DAC. In a typical single-bit configuration, the digital input signal is converted into a binary sequence by a 1-bit quantizer, and the binary sequence is converted into the analog output signal by a 1-bit internal DAC. In a typical multi-bit configuration, the digital input signal is quantized to three or more quantization levels by a multi-bit quantizer to generate a digital sequence, which is subsequently converted into the analog output signal by a multi-bit internal DAC.
Although the conventional single-bit sigma-delta DAC is typically highly linear due to the inherent linearity of the 1-bit internal DAC, the single-bit sigma-delta DAC has drawbacks in that its signal range is limited. In contrast, the conventional multi-bit sigma-delta DAC has a wider signal range. However, the non-linearity of the multi-bit internal DAC included in the multi-bit sigma-delta DAC can cause increased signal distortion and noise. For this reason, suitable trim calibration and dynamic element matching techniques are frequently employed to improve the linearity of the multi-bit DAC.
It would therefore be desirable to have an improved sigma-delta modulation technique that may be employed in digital-to-analog converters and avoids the drawbacks of the above-described conventional techniques.
In accordance with the present invention, an improved sigma-delta modulation technique is provided that may be employed in Digital-to-Analog Converters (DACs) to convert digital input signals into corresponding analog output signals over a wide signal range and with high linearity. The presently disclosed sigma-delta modulation technique achieves such benefits by adaptively quantizing a digital input signal to a reduced number of quantization levels, and correlating the magnitudes of the quantization levels to the amplitude of the digital input signal. The quantization levels may then be provided to a DAC to produce an analog output signal that corresponds to the digital input signal.
In one embodiment, the sigma-delta modulation technique is employed in a sigma-delta DAC that comprises a digital sigma-delta modulator and an internal DAC. The sigma-delta modulator includes a sigma-delta core circuit, a variable quantizer, and a quantizer controller. The sigma-delta core circuit receives a digital input signal and provides its output to the variable quantizer, which in turn provides its output to the internal DAC and to the sigma-delta core via a feedback path. The sigma-delta modulator adaptively quantizes the digital input signal to a predetermined number of quantization levels.
In the preferred embodiment, the sigma-delta modulator is configured for adaptively quantizing the digital input signal to 2 or 3 quantization levels. The quantizer controller controls the variable quantizer to correlate the 2-3 quantization levels to the amplitude of the digital input signal. To that end, the quantizer controller receives the digital input signal, monitors the amplitude of the digital input signal, and controls the variable quantizer to adjust the magnitudes of the quantization levels based on the input signal amplitude. As the amplitude of the digital input signal increases (decreases), the magnitudes of the 2-3 quantization levels are suitably increased (decreased). The internal DAC then receives all of the quantization levels from the variable quantizer in successive groups of 2 or 3 levels, and produces an analog output signal therefrom that corresponds to the digital input signal. The internal DAC is configured to be highly linear within each group of quantization levels, but may provide reduced linearity between the groups of levels.
By adaptively quantizing a digital input signal to 2 or 3 quantization levels, correlating the magnitudes of the 2-3 quantization levels to the amplitude of the digital input signal, and successively providing all of the resulting quantization levels one group of 2-3 levels at a time to an internal DAC to produce a corresponding analog output signal, digital-to-analog signal conversion can be achieved over a wide signal range and with high linearity.
Other features, functions, and aspects of the invention will be evident from the Detailed Description of the Invention that follows.